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preliminary rev. 0.7 1/99 copyright ? 1999 by silicon laborato ries SI3000SSI-EVB-07 SI3000SSI-EVB e valuation b oard f or the s i 3000 with the s tandard s erial i nterface description the SI3000SSI-EVB provid es the modem system designer an easy way to evaluate the si3000 solution. power is supplied through two terminal blocks, v d and v a . this allows for 5-v or 3.3-v operation of the evaluation board. features the SI3000SSI-EVB in cludes the following: ? rj-11 interface to handset ? rj-11 connections to phone line and modem ? microphone, speaker interfaces ? line in, line out interfaces ? buffered digital i/o interface to dsp or asic ? recommended layout for key components ? easy power connection for 5 v or 3.3 v operation ? easy power connection for handset ? flexible mclk scheme ? user selectable serial mode ? support for daisy chain operation ? motherboard?daughter card connection function block diagram modem dsp or asic digital i/o si3000 handset select master board daughter card master board line rj11 phone line handset line in line out speaker out mic in motherboard v d supply 12 volts motherboard to daughterboard line level audio i/o external i/o
SI3000SSI-EVB 2 preliminary rev. 0.7 functional description the SI3000SSI-EVB provides an easy way to evaluate the si3000 solution. this si3000 device also supports the connection of multiple devices on a single serial interface. the evaluation board provides a straight forward means of evaluating this feature. the evaluation board consis ts of the si30xxssi-evb motherboard figure 8 / figure 9 and the si3000dc-evb daughter card figure 3 / figure 4 . the si30xxssi-evb can be used with other silic on laboratories daughter cards, such as the si3034dc-evb. contact a silicon laboratories representative for more information. in this document, the si3000dc-evb is occasionally referred to ?daughter card ?, and the si30xxssi-evb as the ?motherboard?. the SI3000SSI-EVB refers to the system which consists of both the ?motherboard? and ?daughter card.? motherboard?daughter card connection jp1 and jp2 on the daughter card are used to connect to the motherboard. jp1 is a 3x8 socket connection to the digital signals of the si3000. in addition, the v d power of the motherboard (j2) is routed to this socket and supplies the power to the daughter card. jp1 connects to jp7 of the motherboard. jp2 is a 2x5 socket connection to the tip and ring and chassis ground of the line interface to the handset selection circuitry. jp2 connects to jp8 of the si30xxssi-evb. power supply power is supplied to the SI3000SSI-EVB by means of j2, on the motherboard, when the board is used in stand-alone mode. if multiple boards are cascaded together, refer to the section on daisy-chain operation for the power supply requirements. j2 is a euroblock header which allows for connection to a bench power supply. j2 provides the power for all devices connected to the v d node. j2 can nominally be 3.3 v or 5 v. note that u3 and u4 can operate from either 3.3 v or 5 v. if y1 is used, it must support 3.3 v operation if v d = 3.3 v. j3 is used to supply power to v a . however, v a is not used in conjunction with the si3000dc-evb. diodes d4 and d5 on the motherboard are used to protect the SI3000SSI-EVB ag ainst over-v oltage or accidental terminal reversal. they are rated at 6.8 v. clock generation the si3000 requir es an mclk input. the evb provides two options for this requirement. mclk can be provided via pin 1 of jp4 (on the motherboard) from the target system or from an oscillato r installed in y1 (on the motherboard). jp3 (on the motherboard) selects the mclk source to the si3000 . in the y1 position, the oscillator installed in y1 is connected. if 3.3 v is the vd supply, y1 must be a 3.3 v oscillator. in the jp4 position, the clock on jp4 is connected. valid mclk frequency ranges from 1 to 60 mhz. if multiple boards are cascaded together, refer to the section on daisy-chain operat ion. only the master board will need an mclk from y1 or jp4. optional call progress speaker this feature on the si30xx ssi-evb is used in conjunc - tion with the si3034/35 evalua tion boards, but is not uti - lized by the si3000. reset circuit the si3000 requires an active low pulse on reset following power up and whenever all registers need to be reset. typically, the target system generates this signal and supplies it on pin 9 of jp4 (on the motherboard). for development purposes, the SI3000SSI-EVB includes a rese t push button, sw1, that is a logic or (active low) wi th the reset signal from the target system. u4 (of the motherboard) provides the reset logic and serves as a buffer. this circuit is not necessary in a production design. if multiple evbs are cascaded together, the reset signal should be generated by the master board. using the sw1 pushbutton on slave bo ards will only reset that slave board and slave boards further down the chain. serial modes the si3000 supports two different serial modes for a glueless interface to many standard dsp and asic serial ports. the serial mode of the si3000 can be selected by jp1 and jp2 on the motherboard. table 1: si3000 serial modes m1 m0 mode gnd gnd fsync frames data gnd v d fsync pulse starts data frame v d gnd slave operation v d v d reserved
SI3000SSI-EVB preliminary rev. 0.7 3 several additional signals are required for proper operation of the serial interface. as mentioned in the clock generation section, an mclk must be provided for the si3000 to operate. fsync, sclk, sdi and sdo are also required signals to operate the si3000. fsync provides the sychronization for the audio samples. this signal operates at the sample rate. a high to low transition marks the beginning of a new frame. sclk is an output of the si 3000 providing the bit clock for the audio samples. data is valid on the falling edge of sclk following a fsync start transition. sdi is audio samples to be transmitted and sdo is audio samples received. the serial port signals are also used during a secondary frame to read and write the internal registers of the si3000. refer to the si3000 data sheet for more details on internal registers and how to read and write those registers. when using the board in stand-alone mode (single), set the motherboard switches as follows: sw2 = 1 and sw3 = 1. figure 1 shows a typical configuration in stand-alone mode. figure 1. stand-alone connections daisy-chain operation the si3000 supports an additional serial mode which places the device in a slave mode. this serial mode is accomplished by m1 = v d and m0 = gnd. the SI3000SSI-EVB can esse ntially be used in two modes: stand-alone (single) and slave. ta b l e 2 shows the configurations necessary for each mode. in addition to jp1 and jp2 (which control the serial mode of the local si3000), sw2 and sw3 are used to route the digital signals to ensure proper connection. the SI3000SSI-EVB can be connected as a slave through jp6. figure 2 shows the connection of a si3034ssi-evb as a master in daisy-chain mode. see the si3034ssi-evb data sheet for more details. figure 2. daisy-chain connections the dsp or asic target system connects directly to the master board. only the master board needs a connection to a power supply. v d is routed through jp5 and jp6. when the SI3000SSI-EVB is us ed as a slave board, the serial mode must be m1 = v d and m0 = gnd. be sure to configure sw2 and sw3 appropriately according to ta b l e 2 . line connection the SI3000SSI-EVB has two physical interfaces designed to connect to the phone line. one of the connectors is on the motherboard ( figure 8 ), j1 pins 3 to d s p phone line power supply osc v a v d y1 jp5 jp6 jp3 jp4 rj11 m1 m0 sw2 sw3 12 21 table 2: SI3000SSI-EVB modes configuration sw2 sw3 m1 m0 single 1 1 gnd x slave 2 2 v d gnd to d s p power supply osc v a v d y1 jp5 jp6 jp3 jp4 rj11 m1 m0 sw2 sw3 12 21 jp5 jp6 jp4 m1 m0 sw2 sw3 12 21 master board slave board to modem hdst select rj11 rj11 speaker mic line in line out rj11
SI3000SSI-EVB 4 preliminary rev. 0.7 and 4, while the other connector is on the daughter card ( figure 3 ). these interfaces are equivalent and interchangeable. when using the SI3000SSI-EVB in stand-alone mode, only one of these line interfaces is used. when using the si3000ssi- evb in slave mode, one of the line interfaces is used to connect to the phone line, while the other line interface is used to connect to the master board modem line interface. this way, both the SI3000SSI-EVB and si3034ssi-evb gain access to the phone line without requiring an external phone splitter. handset interface the SI3000SSI-EVB includes a handset interf ace. this interface is located on the daughter card j1 connector pins 9 and 10. a handset can connect directly to the phone line or the the si3000 device. the target system is expected to control the dpdt relay to select the handset connection. when the hands et is connected to the si3000, both the si3000 and handset are disconnected from the phone line. in th is case, the SI3000SSI-EVB supplies dc power to the handset through an external 12 vdc bench supply. the euroblock header, j6, on the daughter card is provided fo r this connection. 24.5 ma of dc loop current is supplied to the handset. in a voice modem applicat ion, the SI3000SSI-EVB is configured in the slave m ode, with an si3034ssi-evb acting as the master board. when this system is in the on-hook state, either the si3034 or the handset can respond to the phone ring and place the system in the off-hook state. if the system software chooses to allow the si3034 evb to go off hook, the handset is excluded from the phone loop and is connected directly to the si3000 evb. voice traffic is handled by the si3000 and system software is responsible for creating a virtual voice connection between the handset and the phone system through the si3000 and si3034 devices. microphone interface a standard 3.5 mm mini-phono connector located on the daughter card connector j2 is used to provide an interface from an external microphone to the si3000. the input impedance to mic input of the si3000 is at least 10 k ? . the si3000 has a programmable pre- amplification to support many input line levels. if jumper jp3 on the daughter card is populated, the microphone can be powered directly from the si3000 mbias output. the mbias output provides a typical voltage of 2.5 volts and can supply up to 5 ma, programmable through an external resistor. for applications that cannot be met by the si3000?s mbias output, the jumper may be removed and an external biasing voltage can be applied to the microphone. speaker interface a standard 3.5 mm mini-phone connector is located on the daughter card connector j3. the si3000 spkrr and spkrl outputs are designed to drive 60 ? loads directly. to drive a 32 ? headset, an external series resistor (30 ?) is needed. driving a 32 ? headset directly may result in reduced thd and dynamic range performance. the maximum voltage swing is 1 vrms for either the left or right speaker drivers. the si3000 speaker outputs have programmable analog attenuation. line input interface a standard rca jack on the daughter card connector j5 is used to provide the line-level audio inputs to the si3000. the si3000 has a programmable pre-amplifier. the input impedance of the linei is at least 10 k ? . the si3000 supports multiple levels of pre-amplification to support various line-levels. line output interface a standard rca jack on the daughter card connector j4 is used to provide the line-level audio outputs from the si3000. the si3000 line out put gain is programmable. the maximum output voltage is 1 vrms.
SI3000SSI-EVB preliminary rev. 0.7 5 figure 3. si3000dc-evb schematic page 1
SI3000SSI-EVB 6 preliminary rev. 0.7 figure 4. si3000dc-evb schematic page 2
SI3000SSI-EVB preliminary rev. 0.7 7 si3000dc-evb bill of materials reference part c1,c3,c6,c8,c11,c12 0.1 uf, 25 v, +/- 20%, 0805, x7r, c0805x7r250104-mne, venkel c2,c4,c9 10 uf, 16 v, +/- 20%, case a, , ta016tcm106mar, venkel c10 10 uf, 25 v, +/- 10%, case c, , ta025tcm106mcr, venkel d1 diode, , , do-35, , 1n4148, rectron jp1 con24, , , 3x8 100 mil, , ssw-108-01-t-t, samtec jp2 header 5x2, , , 5x2 100 mil, , ssw-105-01-t-d, samtec jp4,jp3 header 2, , , 2x1 100 mil, , 68000-402, berg j1 dual rj-11 jack, , , rj11x2, , mtjg-2-64-2-2-1, adam tech j2,j3 phono jack, , , thru-hole, , 161-3504, mouser j5,j4 rca jack, , , thru-hole, , 16pj097, mouser j6 power connector, , , thru-hole 2, , tsa-2, adam tech k1 relay dpdt, 4.5v, , tq2, , tq2-4.5v, aromat l1,l2 ferrite bead, , , 1206, , blm31a601s, murata q1 npn, , , sot-23, , cmpt2222a, central semiconductor r9,r1 0, , , 0805, , cj21-000-t, koa r3,r2 100 k, 1/10w, +/- 5%, 0805, , cr0805-10w-104jt, venkel r4 10 k, 1/4 w, +/- 5%, 1206, , cr1206-4w-103jt, venkel r7 51, 1/4 w, +/- 5%, 1206, , cr1206-4w-510jt, venkel r8 2.2 k, 1/10 w, +/- 5%, 0805, , cr0805-10w-222jt, venkel u1 si3000, , , s016, , si3000, s ilicon laboratories u2 lm317lz, , , to-92, , lm317l, sgs thompson
SI3000SSI-EVB 8 preliminary rev. 0.7 figure 5. si3000dc-evb silkscreen
SI3000SSI-EVB preliminary rev. 0.7 9 figure 6. si3000dc-evb component side
SI3000SSI-EVB 10 preliminary rev. 0.7 figure 7. si3000dc-evb solder side
SI3000SSI-EVB preliminary rev. 0.7 11 board config. sw2 sw3 m1 m0 stand alone master w/ slaves slave 1 1 1 2 2 2 gnd gnd gnd vd vd x 12 3 456 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 footprint of jp7 top v iew m1 m0 mclk sdi fc/rgdt resetb ofhkb sclk fsyncb sdo aout rgdt/fsd vd vd vd j1 rj-11 1 2 3 4 5 6 jp8 header 5x2 12 34 56 78 910 jp7 con24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 jp1 jp2 figure 8. si30xxssi-evb schematic page 1
SI3000SSI-EVB 12 preliminary rev. 0.7 master mode slave mode to slave to master decoupling c ap for u4 decoupling c ap for u3 mclk ofhk fc sdi rgdt fsync sclk sdo signals are labeled with respect to si3035 rst_offb rst_inb rst_offb sclk_out rst_inb sclk_out reset b reset b aout mclk sclk sclk fsyncb sdo sdi fc/rgdt rgdt/fsd ofhkb vd vd va va vd vd vd vd vd vd vd vd vd va vd va j2 power connector 1 2 sw1 + - u5 lm386m -1 3 2 5 6 1 4 8 7 + c18 1uf + c15 100 uf c24 0.1 uf c14 0.1 uf c17 0.1 uf r18 20 k r13 100 r19 3k r11 10 r15 47 k r12 20 k c26 820 pf tp 25 tp 26 j3 power connector 1 2 c21 0.1 uf + c19 22 uf c22 0.1 uf r24 47 k jp6 header 5x2 12 34 56 78 910 d3 c27 0.1 uf y1 osc 8 14 7 11 4 c25 0.1 uf r14 51 r17 51 r16 51 r31 47 k r32 47 k r28 47 k jp4 hdr 5x2 12 34 56 78 910 r30 51 jp3 r20 51 u3 logic 2 3 4 5 6 7 8 9 1 19 18 17 16 15 14 13 12 11 a1 a2 a3 a4 a5 a6 a7 a8 g1 g2 y1 y2 y3 y4 y5 y6 y7 y8 r27 47 k r26 47 k tp 27 r25 47 k c23 0.1 uf jp5 header 5x2 12 34 56 78 910 u4a 74lv 08 1 2 3 u4b 74lv 08 4 5 6 u4c 74lv 08 9 10 8 u4d 74lv 08 12 13 11 sw2 4pd t 2 1 3 5 4 6 9 7 8 12 10 11 d4 6.8 v 2 1 d5 6.8 v 2 1 j4 rca jack 1 2 sw3 dpdt 2 1 3 5 6 4 + c20 22 uf r29 0 figure 9. si30xxssi-evb schematic page 2
SI3000SSI-EVB preliminary rev. 0.7 13 si30xxssi-evb b ill of materials reference part c14,c17,c21,c22,c23,c24, 0.1 uf, 16 v, 10%, 0603, x7r, c0603x7r160-104kne, venkel c25,c27 c15 100 uf, 16 v, 10%, case d, tant, ta016tcm-107kdl, venkel c18 1 uf, 16 v, 10%, case a, tant, ta016tcm-105kal, venkel c19,c20 22 uf, 16 v, 10%, case b, tant, ta016tcm-226kbl, venkel c26 820 pf, 50 v, 5%, 0805, npo, c0805cog500-821jne, venkel d3 diode, 400 ma, 75 v, do-35, , 1n4148, diodes, inc. d4,d5 6.8 v, 6.8 v, , do-15, , p6ke6.8a, diodes, inc. jp1,jp2,jp3 3x1 header, , , 3x1 100 mil, , 68000-403, berg electronics jp4 hdr 5x2, , , 5x2 100 mil, , nsh-10db-s1-t, robinson-nugent jp5 header 5x2, , , 10 pin thru-hole, , tsw-105-08-t-d-ra, samtec jp6 header 5x2, , , 10 pin thru-hole, , ssw-105-02-t-d-ra, samtec jp7 con24, , , 3x8 100 mil, , tsw-108-07-t-t, samtec jp8 header 5x2, , , 5x2 100 mil, , tsw-105-07-t-d, samtec j1 rj-11, , , thru-hole 6, , 154-0l6641, mouser j2,j3 power connector, , , thru-hole 2, , 506-5ulv02, mouser j4 rca jack, , , thru-hole, , 16j097, mouser r11 10, 1/10 w, 1%, 0805, , nrc10f10r0tr, nic components r18,r12 20 k, 1/10 w, 1%, 0805, , nrc10f2002tr, nic components r13 100, 1/4 w, 1%, 1206, , mcr18ezhmfx1000, rohm r14,r16,r17,r20,r30 51, 1/10 w, 5%, 0805, , cr21-510j-t, avx r15,r24,r25,r26,r27,r28, 47 k, 1/10 w, 5%, 0805, , nrc10j473tr, nic components r31,r32 r19 3 k, 1/10 w, 5%, 0805, , nrc10j302tr, nic components r29 0, , , 0805, , cj21-000-t, koa sw1 sw pushbutton, , , thru-hole 4, , 101-0161, mouser sw2 4pdt, , , smt12, , ase42l, alcoswitch sw3 dpdt, , , thru-hole 8, , ase22l, alcoswitch tp25 test point, , , thru-hole, , 151-207, mouser tp26 test point, , , thru-hole, , 151-203, mouser tp27 test point, , , thru-hole, , 151-205, mouser u3 logic, , , 20-pin soic, , cd74lpt541m, harris u4 74lv08, , , so14, , 74lv08d, philips u5 op-amp, , , m, , lm386m-1, national semi y1 osc, , , dip14, , ,
SI3000SSI-EVB 14 preliminary rev. 0.7 figure 10. si30xxssi-evb silkscreen
SI3000SSI-EVB preliminary rev. 0.7 15 figure 11. si30xxssi-evb component side
SI3000SSI-EVB 16 preliminary rev. 0.7 figure 12. si30xxssi-evb solder side
SI3000SSI-EVB preliminary rev. 0.7 17 n otes :
SI3000SSI-EVB 18 preliminary rev. 0.7 n otes :
SI3000SSI-EVB preliminary rev. 0.7 19 n otes :
SI3000SSI-EVB 20 preliminary rev. 0.7 contact information silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: productinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and isocap are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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